In the architecture of the present invention, plural Function Module Boards (FMBs) are connected to an asynchronous transfer mode (ATM) switch core. Each function module board contains one or more data processors, software including a distributed operating system and one or more application programs, and hardware circuitry including among other things an ATM switch port. The ATM switch core includes a number of Row-Column-Units (RCUs), and each ATM switch port is logically connected to one of the RCUs. When an FMB is connected to an ATM switch core slot, that logical connection is established. To coordinate the tasks performed at each one of the function modules, the distributed operating system is executed by the Board Processor(s) BP(s) in each function module. Signaling and traffic information are routed between various ones of the function modules through the ATM switch core. In order to effect such asynchronous communications, each function module needs to know the identity and the location of the other function modules connected to the ATM switch core. In particular, an internal connection or path needs to be established through the ATM switch core to effect selective interprocessor communication.
While such location and identity information and Internal Control Paths (ICPs) between processors could be established manually by a human operator, (using for example DIP switches contained on each function module board), it would be much less laborious and costly if these configuration tasks could be performed automatically. The invention therefore permits the board processors to adaptively self-configure themselves both during an initial start-up and whenever a new or a replacement function module board is to connected to the ATM switch core.
It is therefore an object of the present invention to provide automatic configuration of a plurality of processors associated with an ATM switch.
It is a further object of the present invention to automatically establish internal control paths between processors associated with an ATM switch.
It is a further object of the present invention to automatically configure new processors when they are associated with an ATM switch.
It is a further object of the present invention to automatically configure an array of processors associated with two or more ATM switches.
It is a further object of the present invention to automatically establish internal control paths between processors associated with different ones of the connected ATM switches.
A self-configuring node includes plural function module boards, each having one or more board processors and a corresponding ATM switch port, connected to available slots of an asynchronous transfer mode (ATM) switch. When the node is placed into service, each of the board processors automatically broadcasts an initial message to all of the ATM switch port locations. The initial message includes each board processor's identification and ATM switch port location.
One of the board processors functions as a master processor. After receiving the initial message broadcast by a board processor, the master processor stores that board processor's identification and ATM switch port location in a database and sends an acknowledgment directed specifically to the board processor broadcasting the initial message. From that acknowledgment signal, the board processor recognizes the identity and ATM switch port location of the master processor.
Internal control paths (ICPs) are then established through the ATM switch between processors using the identification and location information stored for each board processor. In a preferred embodiment, the ICPs are mutually established by the master processor and board processors with the master processor establishing one-half of the ICP and the board processor establishing the other half of the ICP. The internal control paths are used by the various board processors to selectively communicate control messages and other information. As an example of the latter, the master processor may download software to one or more of the board processors using the established internal control paths.
Thus, this first example embodiment of the invention permits automatic configuration of a multiprocessor, ATM switch-based node without requiring polling of the board processors by the master processor or human operator involvement in configuring the node. Basic configuration information stored for each board processor includes its identification and ATM switch port location. Other configuration information may also be stored.
In second example embodiment of the invention, a new is function module board is connected to a vacant slot of the ATM switch core, e.g., to add capacity and/or functionality to the node. When the new function module board is added, the board processor broadcasts automatically an initial message including its identification and ATM switch port location. The master board processor receives the initial broadcast message, stores the identification and ATM switch port location included in the message, and sends an acknowledgment. The master board processor and new board processor initially establish an internal control path through the ATM switch core between the new board processor and the master processor. The addition and automatic configuration of the newly-added board processor does not disrupt the operation of the already-configured board processors.
A third example embodiment of the present invention configures board processors in function modules connected to two or more ATM switch cores. For example, a physical link is established between first and second ATM switches through first and second exchange terminal boards (ETBs) connected to first and second ATM switch cores, respectively, i.e., an ETB interfaces to a physical line, e.g., twisted pair, coaxial cable, optical fiber, etc. The operation of each of the exchange terminal boards is controlled using a corresponding board processor. In the array of the board processors connected to the first and second ATM switches, one is designated the master processor, e.g., the master processor is connected to a port of the first ATM switch.
The master processor configures the board processors in both the first and second ATM switches. When each of the second board processors broadcasts its initial message to all of the ports of the second ATM switch, the second ETB, which functions as a pseudo-master processor, relays the information to the first ETB over the physical link. The first ETB "translates" that information and provides it to the master processor.
The master processor stores the translated information, and acknowledges the initial message from the broadcasting processor connected to the second ATM switch via the first and second ETBs and the physical link. In doing so, the master and board processors mutually establish internal control paths through the first and second ATM switches. Some of the internal control paths being routed over the physical link by way of the first and second ETBs. Thus, through the use of the physical link and the first and second ETBs, the board processors connected to the first and second ATM switch cores are automatically configured and effectively operated as if all the processors were connected to the same ATM switch core.
These and other objects and advantages of the present invention are described more fully below in conjunction with the drawings and the detailed description of the invention.